A novel ZVS full-bridge cascaded step-up DC-DC converter with resonant auxiliary circuit for high voltage-gain applications

High conversion ratio dc-dc converters have received significant attention in renewable energy systems, primarily due to their necessary high-gain characteristics. This research proposes a high step-up ratio full-bridge resonant cascaded (FBRC) dc-dc converter designed for use in photovoltaics (PV), fuel cells (FC), electric vehicles (EV), and other low-voltage output energy sectors to achieve high voltage gain. This converter contains a full-bridge cell with a boost input inductor, a diode-capacitor cascaded stage that replaces the transformer as a voltage multiplier and an inductor-capacitor (LC) parallel-series resonant network across the FB terminal. One of the strategic features of the converter is its high voltage step-up characteristic combined with lower duty cycle operation that limits the maximum current through the active devices, making it particularly suitable for systems that generate low output voltage. In addition, zero-voltage switching (ZVS) is achieved during the turn-off and turn-on operation of the FB switches from 25% to full load, thereby lessening the switching losses. Moreover, the diminished necessity for passive components and the decreased voltage stress on both active and passive devices lead to the use of smaller and more cost-effective components. The theoretical analysis of the proposed converter is validated using a 500 W laboratory-scale prototype wherein high-performance SiC-based MOSFETs have been utilized as switching devices. It offers reduced ripples, with input current ripple at 5% and output voltage ripple at 0.76%. When the load is 400 W and 60 V as the input voltage, the maximum efficiency is found 95.8% at 400 V output voltage. The proposed dc-dc converter, with its high voltage gain and reduced component stress, shows significant promise for application in renewable energy systems.


Introduction
In response to the escalating global energy demand, the use of renewable energy is expanding day by day.Due to its reliability and environmentally friendly nature, governments and policymakers have also prioritized the development of new technologies to address energy needs.
Although renewable energy systems like photovoltaic (PV), wind, and fuel cells (FC), etc. have gained significant momentum [1][2][3][4], the main obstacle to their growth consists in the low power conversion efficiency.On one hand, the output voltage of both the PV module and fuel cell is very low and the PV power output is directly affected by the diurnal changes in solar intensity.Consequently, a higher-voltage step-up dc-dc converter is necessary to amplify the output and ensure compatibility with other devices or applications [5,6].Furthermore, there is a demand for greater voltage-gain dc-dc converters in other applications, in addition to the domains described before.Several instances include offshore wind energy [3], electric, hybrid electric or fuel-cell vehicles [7][8][9], power systems integrating both medium-and high-voltage DC (MVDC and HVDC) [10,11], and various other applications relying on fuel cells [12].
High step-up dc-dc converters can be categorized based on their active switches, isolation state, level of efficiency, voltage-gain technique, etc. [13][14][15].Each group has some pros and cons.In recent times, a lot of research has been carried out to build non-isolated (transformerless) topologies to attain high gain [16][17][18].These are easier to build with a higher power density (in the absence of a transformer), cost-effective, and simple operation.They are appropriate for applications where electrical isolation is not a primary concern and lower power applications.
Several new research has been performed using high turns ratio transformers to make a high-gain converter for renewable power [19][20][21].On the other hand, isolated boost converters with transformers have several merits including the provision of electrical isolation between the input and output, resolving ground loop problems and safety issues, suitable for high-power applications, and improving voltage regulation and less electromagnetic interference (EMI).These characteristics enable their integration into high-power systems with enhanced stability and robust control.Nevertheless, they encounter several challenges, including increased size due to additional isolation components, higher cost, winding losses, elevated leakage inductance, and reduced efficiency as pointed out in [22].These issues have been tackled by using more active switches for active clamping and some expensive and complicated control methods [23][24][25].
The PWM dc-dc converters have the most basic isolated designs, which include the Forward, the Flyback, the Push-Pull (PP), and the conventional C ´uk, Sepic, and Zeta with galvanic isolation.However, their static dc voltage step-up ratio isn't as good as it used to be, and the input current usually has a lot of noise.Also, there is a lot of voltage stress on their output diodes, so they need diodes with a high breakdown voltage rating [26,27].
Depending on the application, resonant dc-dc converters have advantages and disadvantages in terms of expense, complication, compactness, dependability, and efficiency.Better transformer utilization and strong dc voltage gains are provided by the current-fed resonant converter in [28].Besides, the transformer's leakage inductance is integrated into the converter's basic workings as a resonant network, aiding in zero-current switching (ZCS) for the frond-side inverter switches.With its less component use, this converter is appropriate for low-power systems.In [29], a flyback topology for an RF, ZVS resonant PP converter is presented.It exhibits a high power density despite the high component count.More costs are required to reach a very high power density.This converter offers the same dc voltage gain ratio as the RF ZVS PP quasi-resonant converter in [30].However, both converters' dependability declines and complexity rises as a result of their three winding transformers and numerous switches [29,30].
Many investigations have been conducted to get high gain by the application of the principles of diode-capacitor or diode-inductor cells [31][32][33][34].Their sturdy and straightforward structures make it easy to use simpler control strategies.However, when voltage-cascaded stages increase, the majority of these converters experience increased voltage stress.For instance, the converter in [31], uses a voltage multiplier network based on FB cascaded diode capacitors to achieve a high voltage step-up ratio without the need for high-duty cycle operation.Furthermore, the voltage stress is comparatively smaller and is independent of the change in cascaded stages for capacitors, diodes, and switching devices.Nevertheless, this topology is not widely used because of the hard switching, low efficiency, and large boost inductance.A modified version of the converter [31], is suggested in [35], with an additional small inductance added between the FB legs.It provides cascaded stage independence, lower voltage stress, and a high conversion ratio.Additionally, by using a smaller cascaded capacitance and lower boost inductance, it achieves a slightly greater efficiency than the converter in [31].However, soft switching operation was not achieved by this architecture.
The literature review indicates a clear and ongoing need for resonant soft-switching high conversion ratio dc-dc converters that can provide substantial voltage gain at lower voltage stress with low ripples, specifically for low-voltage output energy sectors.This article proposes a full-bridge resonant cascaded (FBRC) dc-dc converter that offers minor ripples in output voltage and input current, compactness, improved efficiency, and less voltage stress on the FB switches.Moreover, it provides zero switching losses through the ZVS of the FB switches.Therefore, for low-voltage output sources like fuel cells, PV panels, and other renewable energy systems, this high-voltage step-up ratio converter can be a suitable component.The subsequent sections of this article are structured as follows: Section 2 elucidates the principles governing converter operation.In Section 3, a comparative analysis of performance is provided, coupled with discussions on the design considerations and parameter selection.Section 4 offers a concise depiction of the control mechanism employed in the proposed converter.Section 5 delineates the experimental results and their interpretation.The concluding remarks of the article are presented in Section 6.

Converter operation
The full-bridge cascaded (FBC) converter reported in [35] has been improved by adding a resonant auxiliary circuit in place of the parallel inductor to achieve higher efficiency and ZVS operation.This section describes how this converter operates based on its different operating modes showing the current flow routes and optimal waveforms for each mode.The following presumptions are taken into account to streamline the analysis and operation smoothly: 1.The converter operates in steady-state mode with n-stage of cascaded multiplier and continuous conduction mode (CCM).
2. No losses and ripple are taken into account; all the passive and active devices are ideal.
3. Because every capacitor utilized in this architecture is sufficiently large, every capacitor's voltage is the same, except the first capacitor's (C 1 ) value, which is half that of the other capacitors.
Fig 1 shows the developed high step-up FBRC converter.Low-voltage DC sources such as PV modules, FCs, batteries, DC power supplies, etc., can be used as the converter's input.The converter in Fig 1 is built using an n-stage cascaded voltage multiplier, a resonant branch, and an FB cell comprising four switches designated S U1 , S U2 , S L1 , and S L2 , along with a boost input inductor (L s ).The resonant inductor (L r1 ) is connected in series with the parallel capacitor (C r )-inductor (L r2 ) branch placed between the ac terminals (A and B) of the FB module.A single pair of diodes and a couple of capacitors make up a cascaded stage, whereas an n-stage contains 2n = N diodes and a comparable number of capacitors.
The resonant converter's switching frequency is maintained close to its resonant frequency for optimal performance.Two distinct, independent frequencies are used to turn on and off the FB switches.Two distinct frequencies, designated as f SU and f SL , respectively, are used to operate the two upper switches (S U1 and S U2 ) and the two bottom switches (S L1 and S L2 ).A higher current can be supplied by the resonant branch to charge the FB switches' bypass capacitors, achieving ZVS for both the upper and lower switches.To get the desired performance, the f SU is kept substantially lower than the f SL in this study, while the f SL is chosen as close to the resonant frequency as feasible.While f SU is maintained at a fixed value to achieve the necessary output voltage ripple, the duty cycle of f SL is adjusted within the resonance region to control the output voltage, V o .As seen in Fig 2, in this mode, the voltage across the FB terminal drops to zero, v b = 0 throughout the interval t o < t < t 1 .As a result, the resonant current is fixed as: where i r current passes through the resonant branch.On the other hand, the input boost inductor current can be found as follows: where i SL1 is the current passes through the switch, S L1 , and the resonant branch voltage is  The voltage across the FB terminal at this step, v b = V o /2n occurs at the time interval t 1 < t < t 2 .The expression for the input inductor current i Ls is: where V i and v b stand for the voltages at the input dc source and FB output terminals A and B, respectively.The FB terminal voltage v b can be calculated as follows: where v r1 and v Cr are the voltages across the resonant circuit inductor and capacitor respectively.Therefore, the resonant voltage and current can be expressed as, i r is the resonant current, if the initial voltage v r1ðt 1 Þ ¼ 0, then Eq (8) becomes: where the angular resonance frequency, o r ¼ 1= ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi L r1 ðC r jjL r2 Þ p and resonant impedance, Z r ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi L r1 =ðC r jjL r2 Þ p .Therefore, the voltage across the resonant capacitor, v Cr : Combining Eqs ( 9) and ( 11), From Eqs ( 5), ( 6) and ( 9), As can be seen in Fig 2, there is an equal flow of current (i b ) through diodes D 2 and D 4 throughout this time.Diode current may therefore be represented as follows using Eqs ( 5) and ( 13): Mode II-c (t 2 < t < t 3 ): during this interval Mode I will recur, meaning that switches S U1 and S L1 are turned ON, and the other switches (S U2 and S L2 ) and all the multiplier diodes are switched OFF.As a result, each current expression will be the same as what is mentioned in Mode I.
Mode II-d (t 3 < t < t 4 ): Mode II and Mode I will repeat one after the other during this period.Therefore, all of the current and voltage expressions should be the same as indicated above.
Mode III (t 4 < t < t 5 ): During this phase, switch S U2 and S L2 are turned on, and the opposite switches (S U1 and S L1 ) and all cascaded circuit diodes are turned off.The high-frequency operating switches S L1 and S L2 also function under ZVS conditions.The input dc voltage charges the boost input inductance (L s ), the resonant inductor (L r ), and the capacitor via the switches S U2 and S L2 , and the S L1 switch's bypass diode, respectively.As revealed in Fig 4(A), the bottom capacitors (C 4 and C 2 ) transfer energy to the load similarly to Mode I, while C 3 and C 1 stay in the floating position.In this mode, the resonant branch current (i r ) is fixed during the interval t 4 < t < t 5 , and the voltage across the FB terminal drops to zero, i.e., v b = 0. Therefore, the boost inductor current can be calculated as: where i SL1 is the current which flows through the switch, S L2 .Mode IV: S U2 and S L1 are switched ON, and S U1 and S L2 are turned off.The inductances and input dc source transfer energy to the diode-capacitor voltage multiplier circuit through the conducting of diodes C 3 and C 1 .In Mode IV-a, as seen in During the interval t 5 < t < t 6 , voltage across the FB terminal is v b = V o /n, and the current i b can be expressed as follows: The FB terminal voltage, v b can be determined as: i r is the resonant current, then Eq (20) becomes: As a result, voltage across the resonant capacitor v Cr : From Eqs ( 17), ( 18) and ( 21), According to Fig 4(B), i b , current flows through both diodes (D 1 and D 3 ) equally at this time.Therefore, from Eqs ( 17) and (24), diode current can be expressed as: Mode IV-c (t 6 < t < t 7 ): Mode III will recur in this interval, with switch S U2 and S L2 turned ON; and the other switches (S U1 and S L1 ) as well as all of the voltage multiplier network diodes are switched OFF.Hence, every current expression will be the same as what Mode III states.
For t 7 < t < t 8 , Mode IV-d: Modes IV and III will repeat in turn during this period.Therefore, every statement for current and voltage expression will ideally resemble those operating modes.The cycle will then begin once more after this.

Parameter design and selection
The full-bridge resonant cascaded (FBRC) converter's dc voltage gain is contingent on the duty cycle, resonant frequency, and high-frequency switches switching frequency.The link between these variables is explained in this section, along with how different components are designed taking into account their stress and permitted input current and output voltage ripples.Furthermore, the range of ZVS operation of the FB switches has been explained along with the resonance circuit across the FB terminal that supplies the resonance current needed to accomplish ZVS has also been described.The resonance current required for the FB switches to achieve ZVS is provided by the resonant circuit in series with an inductor (L r ) and a capacitor (C r ) across the FB terminal.Furthermore, the converter can operate under ZVS state from full load to 25% load to this design.

DC voltage conversion ratio and duty cycle
The time durations (t o -t 1 ) and (t 1 -t 2 ) are precisely equivalent to the time spans dT SL and (1-d) T SL , as seen in Fig 2, where d denotes duty ratio, and T SL (1/f SL ) is the switching signal period of switches S L1 and S L2 .To express the dc voltage conversion ratio of this converter, one can substitute dT SL and (1-d)T SL for the time in Eqs ( 2) and ( 6), and then use the volt-second balance strategy upon the boost inductor (L s ): where k r = f SL /f r is the resonant constant, and f r is the resonant frequency.In a resonant converter, the switching frequency should ideally match the resonance frequency or k r = 1.In contrast, the switching frequency, f SL is controlled to maintain regulated output voltage.Therefore, the resonant constant value is kept as k r = 0.7~1.1 for ±10% variation of f SL .The voltage step-up gain of the suggested FBRC converter is compared with a few other converters described in the literature.It can be observed from Fig 5 that the voltage gain of this converter is higher than the other converters concerning the duty cycle.Also, although the component counts of this converter are slightly higher, the voltage step-up gain is higher compared to other converters except the converter described in [35], as shown in Fig 6.

Inductor selection
One important component of the suggested converter's design that affects how much the input current ripples is the boost inductor.A fairly common nonlinear phenomenon is the PV array's output changing the environmental conditions change.The suggested converter is made in a way that makes it ideal for a similar PV array.Nevertheless, ripple current has a massive impact on the PV array and significantly reduces its efficiency.The duty cycle must be raised as the L s grows to control the output voltage and its ripple.Thus, the lowest possible input current ripple is taken into account together with the inductor's size and cost.Boost input inductance (L s ) can be determined as follows: where the input current ripple percentage and the maximum input current are designated by Δi Ls.pk and I Ls.pk , respectively.From Eq (27) it is realized that this ripple relies on the boost input inductance and the operating frequency (f SL ) of S L1 and S L2 for a given voltage gain (M v ) and duty cycle (d).The correlation between these factors is presented in Fig 7, where the solid line displays the boost input inductance versus input current's ripple at the operating frequency, f SL is 80 kHz, and the input ripple vs this frequency is revealed by the triangle marked (dashed) line at inductance of L s = 500 μH.In all scenarios, the current ripples are the same and amount to 5%.Hence, the boost inductor for this converter is assumed to be 500 μH for f SL and Δi Ls.pk are 80 kHz and 5%, respectively.The boost input inductance's (L s ) maximum stored energy can be computed as follows: The value can be computed as follows in the case of parallel inductance: where I Lp.pk and Δi Lp.pk indicate as the parallel inductance's peak current and its percentage of ripple.The parallel inductance's (L p ) maximum stored energy can also be computed as follows:

Capacitor selection and voltage stress
Except for the first capacitor, which has a voltage that is half of the others, all of the cascaded capacitors used in this design are suitably large and uniform in size, as was mentioned in the section above.Based on these presumptions, each capacitor's voltage is as follows: where the voltage of each capacitor, except the first (C 1 ), is v c , and v cj represents the jth Combining Eqs (31) and (32) the voltage of each capacitor of the voltage multiplier circuit for the n-stage can be stated as follows: Therefore, according to Eq (33), the voltage multiplier capacitor's maximum voltage stress is V o.pk /2n, and for the first capacitor, it is V o.pk /n, in which V o.pk represents the output voltage's peak value.The fifth row of Table 1 lists the voltage stresses for a single capacitor of this and alternative converter topologies.The value of the duty cycle and input dc voltage, as indicated in Table 1, are the only factors that affect the capacitor voltage stress for the recommended converter and the converter described in [31].In contrast, the number of cascaded stages (n) of the other converters greatly influences the capacitor voltage stress.
Fig 8 illustrates voltage strains on the capacitor for this converter and a few others at a constant duty ratio, d = 0.5 and a constant output voltage, V o = 380 V. Therefore, it can be seen from the voltage step-up gain equation of these architectures listed in Table 1 that the number of stages increases, the required input voltage declines.For instance, if there are two stages, (n = 2), and constant d = 0.5 and constant V o = 380 V, the proposed converter input voltage is 31.67V, whereas the converter reported in [34] requires a higher voltage, which is 76 V.As a result, the suggested topology has a lower capacitor voltage stress than the later one and also lower compared to the other converters up to the number of voltage multiplier stages, n = 2 as displayed in Fig 8.The voltage across the capacitors about duty ratio can be stated as follows from Eqs (33) and ( 26) by considering the ideal value of k r = 1: ( As can be observed from Eq (34), unlike the other converter topologies described in the literature, the individual capacitor voltage of this converter fluctuates with variations in the V i and d rather than the number of voltage multiplier stages.Although all capacitor voltages are equal in theory, it is impossible to ignore the voltage drops and ripples that occur when a capacitor is loaded.The ripple voltage of each specific capacitor is as follows, according to the

Voltage stress Switch
where T SU and I o.av stand for the time duration of the alternating frequency and the average output current, respectively.The ripple of the output voltage for a given current output and the number of voltage multiplier stages can be observed from Eq (35) depending on the gate signal frequency (f SU ) of the upper two switches (S U1 and S U2 ) as well as the foot side capacitance.The stored energy in capacitance can be given by: By submitting Eqs ( 34) and ( 35) into Eq (36), ð2V i ð1 þ dÞ=1 À dÞ 2 ; for j ¼ 2; 3 . . .; N ð37Þ (

Switch's voltage and current stresses
The highest voltage stress of the diode is twice that of the gate switches which is V o.pk /2n, and the extreme stress of current is I b.pk /n, where I b.pk is the peak current input of the voltage multiplier circuit.Two diodes are on at once.The switch's voltage stress is represented in Fig 11 .It is lower for this suggested converter than others except the converter reported in [39].Table 2 represents the performance such as the output power, efficiency, voltage ripple, current ripple, voltage gain, and duty ratio of some boost-type dc-dc converters suitable for renewable energy (e.g., PV, FC, etc.) applications compared with the suggested converter.The voltage gain is higher for the converter in [40] than the others, whereas the ON time of the switch(s) is kept lower for the proposed converter.In addition, the measured efficiency is higher than all other converters.Furthermore, the converter in [41], offers the least output voltage ripple; however, it suffers from poor efficiency at the rated power.The output voltage and input current ripples are much higher in the converter [18] than that of the developed converter.Moreover, the proposed converter's output power, voltage gain, efficiency, and ripples are better than the converter described in [35].

Condition and range for ZVS of the switches
As seen in Fig 3, the ZVS current of switch S L2 is the difference between the bridge current (i b ) and the auxiliary resonant branch current (i r ) at t 2 .On the other hand, as Fig 3(E) illustrates, the ZVS current of switch S L1 is the result of a combination of the bridge current (i b ) and the auxiliary resonant branch current (i r ) at t 6 .Given that the operating frequencies of these two switches are the same (t 1 = t 2 = t 6 ).As a result, these two currents have the same RMS value.Therefore, The following requirements must be met for S L1 and S L2 's ZVS to switch on and off: It is clear from Fig 3 that the RMS current (I SU.ZVS ) flowing through the upper two switches (S U1 and S U2 ) has the same magnitude as I SL.ZVS .However, current flow through these switches for a longer period than t 1 is approximately 8.89 times longer (8.89 is the frequency ratio of f SL and f SU for this study).Consequently, the lower frequency switches (S U1 and S U2 ) likewise operate securely under ZVS conditions across the whole operational range.

Control technique
This section describes the control technique of the proposed converter in brief. .f SU and f SL are designated as the alternating frequency and modulating frequency, respectively, for the sake of ease.Ideally, choosing these two frequencies as high as possible is necessary to minimize the usage of lower values of passive components (capacitor and inductor) in the circuit.This study achieves the desired output by maintaining a significantly lower frequency for f SU compared to f SL .The output voltage V o is controlled by adjusting the duty ratio of f SL , while f SU determines the ripple of V o .Furthermore, the f SL to f SU ratio must be an odd number (an integer or a fraction).Specifically, if the ratio (f SL /f SU ) is not an even integer F, the voltage across the FB (v b ) will be unidirectional instead of alternating.This is because two switches of the same FB lag, S U1 and S L1 or S U2 and S L2 , will turn on simultaneously at the transition of f SU .

PID controller design
The state-space averaging methodology is commonly employed to design linear controllers for dc-dc converters due to its ability to integrate the advantages of both state-space and averaging methods.It uses the inductor current and capacitor voltage as separate variables.This converter's continuous time-domain transfer function can be expressed using the state-space averaging technique as follows: The parameters' values can be found in Tables 3 and 4, as well as in their respective data sheets.Upon submitting these values, the control to output transfer function at the nominal operating point is determined as: The PID controller, a lead-lag compensator, is extensively employed in feedback control systems.Thus, the PID controller is selected to regulate the proposed converters.The PID controller can be defined as: where e(t) and m(t) represent the input and output of the compensator, respectively.The Laplace transform of the transfer function described in Eq (42) can be expressed as: This continuous time domain transfer function is converted to a discrete-time domain to implement in the DSP controller.Therefore, the digital transfer function of the PID controller can be derived as follows: The z-domain transfer function of the PID controller in Eq (44) needs to be transformed into a difference equation to generate a new duty cycle for the digital PID controller using DSP.The difference equation can be expressed as: where u[k] and e[k] represent the controller output and output error, respectively, for the kth sample.The various parameter values are located in the experiment and data sheets.

Experimental outcomes
To validate the theoretical analysis for the developed FB resonant cascaded (FBRC) dc-dc converter, a 500 W laboratory prototype of two cascaded stages is implemented.The figure of the experimental setup indicating all apparatus is displayed in Fig 14 .To get the intended output voltage, V o = 400 V, a broad range of input voltages (40 ~80 V) is applied.The duty ratio of the gate switching frequency (f SL ) is adjusted between 0.45 ~0.6.The Texas Instrument TMS320F28335 controller generates and controls the switching signals.Tables 3 and 4 list the component values following the design process and the various parameters employed in the developed converter.The dynamic response of this converter for the PID controller to variation in load is represented in Fig 26 .When the load is increased from 50% to 100%, the output voltage first slightly drops before increasing for a few milliseconds (ms) to stabilize at the ideal 400 V.It takes about 32 ms (approx.) for the disturbance to stabilize in total.Similar to this, when the load is reduced from 100% to 50%, the output voltage first increases somewhat before stabilizing.

Loss and efficiency analysis
This subsection provides a concise, step-by-step description of the power loss calculation among the main components and a brief efficiency analysis of the suggested converter.
Initially, the power loss of a MOSFET switching device can be written as follows where P s(mos) and P con(mos) are the MOSFET switching and conduction losses, respectively.Since each FB switch of this converter operates ZVS, the switching loss is optimally negligible.Therefore, we can consider only the conduction loss, and it can be stated as: The variables I 2 rmsðmosÞ and R ds(ON) represents the RMS current flowing through the MOSFET and the ON state resistance of the MOSFET, respectively.Hence, based on the experiential data and datasheet of the C3M0120090D MOSFET utilized in this study, the total power losses of four FB switches can be determined as follows: The power dissipated by a diode can be calculated by multiplying its forward voltage drop, V F , by the average current, I d(avg) , that flows through it during one switching cycle.Therefore, based on the datasheet of the IDH10S120 diode and the average current obtained from the experiment, the diode's (four diodes) total losses may be determined.
The power dissipation of the B32776G4506K000 film capacitor utilized in this study can be computed using the following formula: Hence, the total capacitor power loss will be the sum of four cascaded multiplier capacitors loss and one resonant branch capacitor loss: The inductor loss is the sum of the core loss, P L(core) , and the winding loss, P L(wind) .The calculation of P L(core) involves multiplying the effective volume of the core, V e , by the core loss per unit volume, P (c/v) , according to the following formula: Again, the inductor winding loss can be expressed as: The variables I L(avg) , I L(ac-rms) , I L(pk-pk), and R dc represent the average current, ac rms current, peak-peak ripple current magnitude, and winding dc resistance of the inductor, respectively.The VISHAY IHV15BZ500 and two BOURNS JW MILLER 1130-101K-RC devices are utilized in this study as the input boost inductor and resonant branch inductors, respectively.Therefore, based on the testing results and the inductor data sheet, the total inductor losses can be Therefore, the total calculated power loss of the developed converter is The experiment yielded a measured power loss of 16.80 W, which is marginally lower than the above-calculated power loss.The power loss for the diode and capacitor is determined based on a temperature of 25˚C.Nevertheless, the temperature at the junction of these devices rises as power is dissipated, reducing the diode's forward voltage drop and the capacitor's equivalent series resistance (ESR).Consequently, there is a decrease in power loss.The loss   (40,60, and 80 V).The input and output currents and voltages are measured using two oscilloscope current probes and multimeters to determine the converter's efficiency.The system's peak efficiency is 95.8% when a load of 400 W is connected, and an input voltage of 60 V is applied.This efficiency is achieved when the output voltage is set to 400 V.In addition, Fig 31 presents the effect of the duty ratio on the converter's efficiency.The converter's efficiency is also lower at a low duty ratio because the lower output voltage causes higher current resulting in more power loss.Again, at a higher duty ratio, converter efficiency is also lower.

Conclusion
High-gain dc-dc converters play a significant role in various renewable energy and other systems.This study introduces a novel ZVS full-bridge cascaded step-up dc-dc converter.In addition to comprehensive analytical analysis, a laboratory-scale prototype was designed, constructed, and subjected to experimental testing.The theoretical findings closely align with the observed experimental outcomes of the 500 W prototype converter.In the prototype implementation, high-performance SiC-based MOSFETs have been utilized as switching devices.Furthermore, the PID-based PWM control scheme and the resonant component have been employed to control the turn-off and turn-on operations of the FB switches from 25 to 100% load conditions facilitating zero-voltage switching (ZVS).The application of four such FB switches ensured complete soft-switching (zero switching loss).Additionally, the resonant technique leads to smaller passive components and reduces voltage stress on both active and passive devices.Consequently, this results in smaller and more costeffective devices compared to other converters.Moreover, it offers less ripple in input current (5%) and output voltage (0.76%).From an efficiency standpoint, the converter achieves its maximum efficiency of 95.8% when operated at input and output voltages of 60 V and 400 V, respectively, with a load power of 400 W.
The dc-dc converter proposed in this research achieves an excellent dc voltage conversion ratio (> 10) by preventing excessively high-duty cycle operation of the MOSFET switches, thereby limiting the maximum current flow through the active devices.Hence, the proposed FBRC converter is well-suited for systems generating low output voltage, making it particularly suitable for variable wide input ranges (tested from 40 V to 80 V), commonly found in low voltage systems like photovoltaic (PV), fuel cell (FC), and electric vehicles (EV).

Fig 2
illustrates the main wave shapes of the proposed converter for two cascaded stages and one switching period.It shows the FB MOSFET switching signals, the voltage across the FB terminal (v b ), current i b , the resonance current i r , and the cascaded multiplier diode current I D1 -I D4 .Due to the alternating behaviour of i b , the suggested topology's CCM working approaches can be split into two parts: one for the +ve interval and another for the -ve interval, with corresponding time lengths [T o , T SU /2] and [T SU /2, T SU ].Only one diode conducts at order D 4 followed by D 2 in the positive half-cycle, and only one diode comes in conduction at order D 3 followed by D 1 in the other half-cycle.Furthermore, two operational modes, which are designated as Mode I and Mode II as displayed in Fig 3(A)-3(C) throughout this first half-cycle.Four distinct sections make up Mode II: Mode II-a, Mode II-b, Mode II-c and Mode II-d.As seen in Fig 4(A)-4(C), there are two working modes in the opposite interval of Mode III and Mode IV.Mode IV is further divided into four sub-modes, which are designated as Mode IV-a, Mode IV-b, Mode IV-c, and Mode IV-d. the n-stage diode-capacitor cascaded multipliers for which the proposed converter has undergone mathematical analysis have improved the converter's applicability.Below is a detailed explanation of the circuit operation principles based on these operating modes.Mode I (Fig 3(A)): In this stage, the high frequency switches S U1 is ON and S U2 is OFF, and all of the diodes of the voltage multiplier network are also switched OFF.At t o , the high-frequency gating signals are applied to S L1 and S L2 , and S L1 is turned ON when ZVS conditions are met.Through conducting switches S U1 and S L1, as well as the bypass diode of S L2 , the boost inductor, resonant inductor, and capacitor are charged by the dc voltage source V i .while C 3 and C 1 stay floating, the capacitors C 4 and C 2 provide current to the output.

Fig 4 .
Fig 4. Current flow routes of the developed FBRC converter.(a)Mode III.(b)Mode IV-a.(c) Mode IV-b.https://doi.org/10.1371/journal.pone.0306906.g004 Fig 4(B), the diodes D 3 and D 1 conduct, as a result, the FB current discharges C 2 and charges C 3 and C 1 ; and load is driven by the current of C 4 .In the subsequent Mode IV-b, diode D 1 is in conduction, which causes, C 1 to be charged by i b , the load current is provided by C 4 and C 2 , and when C 3 stays in a floating state as shown in Fig 4(C).

Fig 8 .
Fig 8. Comparison of the voltage stresses on the capacitor of the proposed and other converters.https://doi.org/10.1371/journal.pone.0306906.g008 Fig 9 represents  the correlations between these factors.The solid line in Fig9indicates the capacitance versus ripple voltage at a given operating frequency, f SU is 9 kHz.Additionally, the operating frequency, f SU versus ripple is displayed by the triangle marked dashed line at the given capacitance value, C = 50 μF.The ripple of the output voltage should be the same 0.76% in both scenarios.Therefore, for switching frequency, f SU , is 9 kHz and Δv C, is 0.76%, the capacitance is chosen as 50 μF for this suggested converter.There is a little bit of voltage unbalance in the multiplier capacitor as revealed in Fig 10.At capacitance 50 μF, voltage imbalance is found as 0.2%.

Fig 11 .
Fig 11.Voltage stress on switch of the proposed FBRC converter.https://doi.org/10.1371/journal.pone.0306906.g011 The proposed converter operates similarly to the classic boost converter, except for the alternating voltage (v b ) and current (i b ) generated across the full-bridge terminal.Due to the cost-effectiveness, fast processing speed, and user-friendly application, the DSP chip has generated control signals for the designed converter.The suggested converters utilize a two-independent-frequency variable-duty cycle PWM modulation technique to generate the gate signals.The FB module has four switches, S U1 , S U2 , S L1 , and S L2 , as depicted in Fig 12(A).S U1 (S L1 ) and S U2 (S L2 ) work in a complementary manner, with S U1 's switching frequency denoted as f SU and S L1 's switching frequency marked as f SL , as shown in Fig 12(B)

Fig 12 .
Fig 12. (a) Full-bridge module.(b) Control gate signals of the full-bridge module of the proposed converter.https://doi.org/10.1371/journal.pone.0306906.g012 Fig 13 displays the block diagram of the control technique used in this converter.The voltage sensor measures the output voltage and transmits it to the DSP module.The digital signal processor (DSP) produces switching gate signals for the FB MOSFET by comparing the output voltage (V o ) with the reference voltage (V ref ), using the PID controller technique.

Fig 16 .Fig 17 .
Fig 16.Experimental switching signals of the four FB MOSFET gates.https://doi.org/10.1371/journal.pone.0306906.g016 Fig 27 displays the PID controller's dynamic behaviour in the variations of the input voltage.It shows that when the input voltage is slightly increased, the output voltage rises at first before falling back to its starting value and becoming steady.Furthermore, the experimental output voltage (V o ), current (I o ), and input inductor current (i Ls ) are presented in Fig 28.There is good agreement between the experimental and the simulation outcomes.